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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">TRCCCCTLR, Cycle Count Control Register</h1><p>The TRCCCCTLR characteristics are:</p><h2>Purpose</h2>
        <p>Set the threshold value for cycle counting.</p>
      <h2>Configuration</h2><p>External register TRCCCCTLR bits [31:0] are architecturally mapped to AArch64 System register <a href="AArch64-trcccctlr.html">TRCCCCTLR[31:0]</a>.</p><p>This register is present only when FEAT_ETE is implemented, FEAT_TRC_EXT is implemented and TRCIDR0.TRCCCI == 1. Otherwise, direct accesses to TRCCCCTLR are <span class="arm-defined-word">RES0</span>.</p><h2>Attributes</h2>
        <p>TRCCCCTLR is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="20"><a href="#fieldset_0-31_12">RES0</a></td><td class="lr" colspan="12"><a href="#fieldset_0-11_0">THRESHOLD</a></td></tr></tbody></table><h4 id="fieldset_0-31_12">Bits [31:12]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-11_0">THRESHOLD, bits [11:0]</h4><div class="field"><p>Sets the threshold value for instruction trace cycle counting.</p>
<p>The minimum threshold value that can be programmed into THRESHOLD is given in <a href="ext-trcidr3.html">TRCIDR3</a>.CCITMIN. If the THRESHOLD value is smaller than the value in <a href="ext-trcidr3.html">TRCIDR3</a>.CCITMIN then the behavior is <span class="arm-defined-word">CONSTRAINED UNPREDICTABLE</span>. That is, cycle counts might or might not be included in the trace and the cycle count threshold is not known.</p>
<p>Writing a value of zero when <a href="ext-trcconfigr.html">TRCCONFIGR</a>.CCI enables instruction trace cycle counting results in <span class="arm-defined-word">CONSTRAINED UNPREDICTABLE</span> behavior. That is, cycle counts might or might not be included in the trace and the cycle count threshold is not known.</p><p>The reset behavior of this field is:</p><ul><li>On a Trace unit reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h2>Accessing TRCCCCTLR</h2>
        <p>Must be programmed if <a href="ext-trcconfigr.html">TRCCONFIGR</a>.CCI == 1.</p>

      
        <p>Writes are <span class="arm-defined-word">CONSTRAINED UNPREDICTABLE</span> if the trace unit is not in the Idle state.</p>
      <h4>TRCCCCTLR can be accessed through the external debug interface:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>ETE</td><td><span class="hexnumber">0x038</span></td><td>TRCCCCTLR</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When OSLockStatus(), or !AllowExternalTraceAccess() or !IsTraceCorePowered(), accesses to this register generate an error response.
          </li><li>Otherwise, accesses to this register are <span class="access_level">RW</span>.
          </li></ul><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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